中圖分類號：TN402 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.256917
中文引用格式： 盧海濤. 一種基帶芯片抗溫漂時鐘控制方法及實現(xiàn)[J]. 電子技術(shù)應(yīng)用，2026，52(2)：35-38.
英文引用格式： Lu Haitao. Method and implementation of clock control for baseband chip against temperature drift[J]. Application of Electronic Technique，2026，52(2)：35-38.

Method and implementation of clock control for baseband chip against temperature drift

Abstract： To address the technical challenge of excessive network timebase tracking error caused by 32 kHz clock temperature drift in the idle state of multi-mode baseband chips, this paper proposes a clock control scheme integrating high-frequency clock extended calibration, two-stage PLL cascade architecture, and hardware automatic switching mechanism. The high-frequency calibration unit collaborates with the Time Processing Unit (TPU) and Low Power Mode (LPM) module to maintain the operation of high-frequency clocks in the idle state for dynamic calibration of 32 kHz clock temperature drift. Meanwhile, the two-stage PLL cascade is utilized to generate high-precision reference clocks, and hardware circuits are employed to achieve glitch-free switching between high and low-frequency clocks.

Key words : multi-mode；temperature drift；calibration；protocol stack；paging reception；dynamic switching；network timebase