基于Palladium AVIP的SoC验证方案
2021年电子技术应用第8期
程 涛
哲库科技(上海)有限公司，上海201210
摘要： 由于片上系统芯片(System on Chip，SoC)规模越来越大，软件仿真速度在一些大的场景测试用例下已经很难满足验证计划时间的要求。现场可编程门阵列(Field Programmable Gate Array，FPGA)原型验证平台容量的限制，以及需要修改时钟树等特性导致FPGA平台并不适合做功耗/性能评估。基于Emulator平台的仿真加速以及功耗/性能评估已经成为一种趋势。可以使用Emulator的加速验证知识产权(Accelerated Verification Intellectual Property，AVIP)替换软件仿真用的验证知识产权(Verification Intellectual Property，VIP)来做仿真加速。以及使用高级微控制器总线结构(Advanced Micro-controller Bus Architecture，AMBA) AVIP来模拟或者监控总线的传输，结合其他工具可以用来做功能/功耗/性能相关的验证工作，大大加速了芯片相关开发验证的进程。
中圖分類號： TN402
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.219803
中文引用格式： 程濤. 基于Palladium AVIP的SoC驗證方案[J].電子技術應用，2021，47(8)：52-55.
英文引用格式： Cheng Tao. SoC verification solution based on Palladium AVIP[J]. Application of Electronic Technique，2021，47(8)：52-55.
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.219803
中文引用格式： 程濤. 基于Palladium AVIP的SoC驗證方案[J].電子技術應用，2021，47(8)：52-55.
英文引用格式： Cheng Tao. SoC verification solution based on Palladium AVIP[J]. Application of Electronic Technique，2021，47(8)：52-55.
SoC verification solution based on Palladium AVIP
Cheng Tao
ZEKU Technology(Shanghai) Co.，Ltd.，Shanghai 201210，China)
Abstract： Due to the increasing scale of the chip, the EDA simulation speed has been difficult to meet the schedule requirements in some large scene cases. At the same time, the capacity of the FPGA prototype verification platform is limited, and some clock trees need to be modified and are not suitable for power/performance evaluation. Simulation acceleration and power analysis and performance evaluation based on Emulator platform have become a trend. Based on the emulator AVIP to simulate or monitor related bus transaction can be used to do the related work of function/power/performance which can greatly accelerated the process of chip development. The test cases developed based on MIPI AVIP for verifying MIPI or using MIPI to verify the internal image processing module achieves dozens of times of acceleration ratio and greatly improves the simulation speed. As well as using AVIP to simulate and monitor the behavior of related modules，can get the netlist power data and performance data. It has made an important contribution to the functional verification and power/performance optimization of the chip.
Key words : Emulator；AVIP；simulation acceleration；power analysis；performance estimation
0 引言
本文主要聚焦于消費電子類的SoC芯片驗證領域，為芯片驗證過程中遇到的功能、功耗、性能驗證方面的一些難題提供了有效的解決方案。相比傳統的驗證方式，基于Palladium AVIP的驗證方案能更加快速高效地達成驗證目的，為芯片按時成功流片提供了強有力的保障。
本文詳細內容請下載:http://m.tom3567.com/resource/share/2000003699，
作者信息:
程 濤
(哲庫科技(上海)有限公司，上海201210)
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