Cirrus公司的CS53L30是高性能低功耗四路ADC,其ADC輸入具有多種模式如模擬或數(shù)字麥克風(fēng)或線路輸入,差分,假差分或單端輸入,數(shù)字處理特性包括音量控制,靜音,可編程高通濾波器和兩個(gè)數(shù)字麥克風(fēng)接口等.主要用在語音識(shí)別系統(tǒng),高端電話系統(tǒng),錄音機(jī),數(shù)碼相機(jī)和攝像機(jī).本文介紹了CS53L30主要特性,框圖, 模擬和數(shù)字麥克風(fēng)連接圖,以及評(píng)估板CBD53L30主要特性,框圖,電路圖和PCB元件布局圖.

The CS53L30 is a high-performance, low-power, quad-channel ADC. It is designed for use in multiple-mic applications while consuming minimal board space and power.

The flexible ADC inputs can accommodate four channels of analog mic or line-input data in differential, pseudodifferential, or single-ended mode, or four channels of digital mic data. The analog input path includes a +10- to +20-dB boost and a –6- to +12-dB PGA. Digital mic data bypasses the analog gain circuits and is fed directly to the decimators. Four mic bias generators are integrated into the device. The device also includes two digital mic serial clock outputs.

The CS53L30 includes several digital signal processing features such as high-pass filters, noise gate, and volume control.The device can output its four channels of audio data over two I2S ports or a single TDM port. Additionally, up to four CS53L30s can be used to output up to 16 channels of data over a single TDM line. This is done by setting the appropriate frame slots for each device, and each device then alternates between outputting data and setting the output pin to high impedance.

The CS53L30 can operate as a serial port clock master or slave. In Master Mode, clock dividers are used to generate the internal master clock and audio clocks from either the 6-/12-MHz, 6.144-/12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz master clock.

The device is powered from VA, a 1.8-V nominal supply and VP, a typical battery supply. An internal LDO on the VA supply powers the device’s digital core. The VP supply powers the mic bias generators and the AFE.

The CS53L30 is controlled by an I2C control port. A reset pin is also included. The device is available in a 30-ball 0.4-mm pitch WLCSP package and 32-pin 5 x 5-mm QFN package.

CS53L30主要特性:

Analog Input and ADC Features
? 91-dB dynamic range (A-weighted) @ 0-dB gain
? –84-dB THD+N @ 0-dB gain
? Four fully differential inputs: Four analog mic/line inputs
? Four analog programmable gain amplifiers
? –6 to +12 dB, in 0.5-dB steps
? +10 or +20 dB boost for mic input
? Four mic bias generators
? MUTE pin for quick mic mute and programmable quick power down
Digital Processing Features
? Volume control, mute, programmable high-pass filter, noise gate
? Two digital mic (DMIC) interfaces
Digital Output Features
? Two DMIC SCLK generators
? Four-channel I2S output or TDM output. Four CS53L30s can be used to output 16 channels of 24-bit 16-kHz sample rate data on a single TDM line.
System Features
? Native (no PLL required) support for 6-/12-MHz, 6.144-/ 12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz master clock rates and 8- to 48-kHz audio sample rates
? Master or Slave Mode. Clock dividers can be used to generate common audio clocks from single-master clock input.
? Low power consumption
? Less than 4.5-mW stereo (16 kHz) analog mic record
? Less than 2.5-mW mono (8 kHz) analog mic record
? Selectable mic bias and digital interface logic voltages
? High-speed (400-kHz) I²C™ control port
? Available in 30-ball WLCSP and 32-pin QFN

主要應(yīng)用:

? Voice-recognition systems
? Advanced headsets and telephony systems
? Voice recorders
? Digital cameras and video cameras

圖1. CS53L30方框圖

圖2. CS53L30典型連接框圖:模擬麥克風(fēng)連接

圖3. CS53L30典型連接框圖:數(shù)字麥克風(fēng)連接



圖4. CS53L30八個(gè)麥克風(fēng)雙CS53L30連接電路圖

評(píng)估板CBD53L30

The CDB53L30 board is a dedicated platform for testing and evaluating the CS53L30, a low-power, quad-channel microphone ADC with TDM output.

To allow comprehensive testing of CS53L30 features and performance, extensive software-configurable options are available on the CDB53L30.

Software options, such as register settings for the CS53L30, are configured with the FlexGUI software, which communicates with the CDB53L30 via USB from a Windows®-compatible computer. In addition, digital I/O headers on the CDB53L30 allow external control signals (from a host processor, for example) to configure and interface with the CS53L30 directly without the use of FlexGUI.

The CDB53L30 also serves as the component and layout reference for the CS53L30.

評(píng)估板CBD53L30主要特性:

• Analog or digital Inputs
— Analog microphone or line inputs via TRS 1/8” jacks
— Digital microphone inputs via stake headers
• Two CS53L30 devices support up to eight channels of phase-aligned audio
• Onboard master clock generator
• S/PDIF transmitter interface via RCA and optical jacks
• External digital I/O via stake headers
— Serial audio port I/O
— Control signal I/O
— External I²C™ control port I/O
• Flexible power-supply configuration
— USB or external power supply
• FlexGUI software control
— Windows® compatible
— Predefined and user-configurable scripts


圖5.評(píng)估板CBD53L30框圖

圖6.評(píng)估板CBD53L30開關(guān)設(shè)置圖

圖7.評(píng)估板CBD53L30電路圖(1)

圖8.評(píng)估板CBD53L30電路圖(2)

圖9.評(píng)估板CBD53L30電路圖(3)


圖10.評(píng)估板CBD53L30電路圖(4)

圖11.評(píng)估板CBD53L30電路圖(5)

圖12.評(píng)估板CBD53L30電路圖(6)

圖13.評(píng)估板CBD53L30電路圖(7)

圖14.評(píng)估板CBD53L30 PCB頂層布局圖
詳情請(qǐng)見:
http://www.cirrus.com/en/pubs/proDatasheet/CS53L30_F1.pdf
和
http://www.cirrus.com/en/pubs/rdDatasheet/CDB53L30_DB1.pdf